Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Window accelerator control
Applicable PC-9801-85, 91, 96, PC-9801B3-E02, PC-9821A-E01, E09, E11
PC-9821Bp, Bs, Be, Bf, Ts, Cs2, Np, Ns, Ne2, Nd, Es, Cf, Cx, Cb, Cx3, Cb3
PC-9821Ap2, As2, An, Ap3, As3
PC-9821Xt, Xa, Xn, Xp, Xs, Xe, Xf, V10, V7, Xa7e, Xb10
Explanation o In the PC-9800 series, the window accelerators used are S3's
86C928 and Vision864, CIRRUSLOGIC's CL-GD5428 and 5430, Matrox's MGA-II and
MGA-2064W, and Trident's TGUI9680XGi and Cyber9320.
o The accelerator chips used by each board are as follows:
-------------------------+--------------------------------------
Board name | Chip installed
-------------------------+--------------------------------------
PC-9801-85･91 |
PC-9821A-E01･E09 | S3 86C928
-------------------------+--------------------------------------
PC-9801-96,PC-9801B3-E02 | CL-GD5428
-------------------------+--------------------------------------
PC-9821A-E11 |
PC-9821X-B01 | MGA-II
-------------------------+--------------------------------------
PC-9821X-B03 | MGA-2064W
-------------------------+--------------------------------------
o Some models have an accelerator chip built into the main body.
-------------------------+--------------------------------------
Model name | Chip installed
-------------------------+--------------------------------------
PC-9821Ap2･As2 |
PC-9821An | S3 86C928
-------------------------+--------------------------------------
PC-9821Xn･Xp･Xs･Ap3･As3 |S3 Vision864
-------------------------+--------------------------------------
PC-9821Bp･Bs･Be･Bf |
PC-9821Cs2 |
PC-9821Ts | CL-GD5428
PC-9821Np･Ns･Ne2･Nd |
PC-9821Es |
SV-98model1･2 |
-------------------------+--------------------------------------
PC-9821Xe･Cf･Cx･Cb |
PC-9821Cx2･Cb2･Xe10 |
PC-9801BX4 | CL-GD5430
SV-98model1A･3 |
-------------------------+--------------------------------------
PC-9821Xa7e･Cx3･Cb3･V10･ |
V7･Xb10 | CL-GD5440
-------------------------+--------------------------------------
PC-9821Ne3･Nd2･Na7･Nx･ |
Lt2 | Cyber9320
-------------------------+--------------------------------------
PC-9821Xa16･Xa13･Xa12･ |
Xa10･Xa9･Xa7･Xv13 | TGUI9680XGi
-------------------------+--------------------------------------
* The FDD models of the PC-9821Ap2, As2, and An do not have an accelerator chip.
* The MGA-II equipped models of the PC-9821Ap2 and An have the PC-9821A-E11
installed in the local bus slot, and do not have a built-in accelerator chip.
* The MGA-II equipped models of the PC-9821Xa, Xt, and Xf, and the PC-9821Xt13
have a PCI video card installed in the PCI slot or a slot dedicated to
window accelerators, and do not have a built-in accelerator chip.
u Window accelerators other than those connected via PCI are controlled via two-stage I/O.
u The S3 86C928 is controlled via memory-mapped I/O.
u I/O 0904h, 0CA0-0CAFh, 0DA4h, 0DA5h, 0DAAh, and FF82h are used to control
the built-in CL-GD5428 and 5430.
u I/O 0904h, 0C50-0C5Fh, 0D54h, 0D55h, 0D5Ah, and 0902h are used to control
the CL-GD5428 in the PC-9801-96 and PC-9801B3-E02.
o For details about accelerator chips, see the documentation for each chip.
Related INT 18h - Function 80h, 81h
I/O 0FA2h
Name Window accelerator board control [INDEX]
Undocumented
Target PC-9801-85, 91, 96, PC-9821A-E01, E09, E11, etc.
Function
[READ/WRITE]
Bit 7-0: Window accelerator internal register
Explanation o Controls the window accelerator board.
o Pairs with I/O 0FA3h to perform two-stage I/O operations.
Related I/O 0FA3h
I/O 0FA3h
Name Window accelerator board control [DATA]
Undocumented
Target PC-9801-85, 91, 96, PC-9821A-E01, E09, E11, etc.
Function
[READ/WRITE]
bit 7-0: Data
------------------+----------------------------------------------
Internal register |Contents
------------------+----------------------------------------------
00h | Read ID value
| bit 7,6: Chip ID (1)
| * Indicates chip ID together with bit 3
| bit 5,4: Bus ID
| 01b = ML bus (MATE local bus)
| 10b = C bus
| 11b = MLNf bus (PC-9821Nf only)
| bit 3: Chip ID (2)
| bit 2-0: Board comp
| * Indicates board revision code
| ----------+-----------------
| Chip ID | Chip
| ----------+-----------------
| 00xx0xxxb | S3 86C928
| 00xx1xxxb | S3 Vision864
| 01xx0xxxb | CL-GD5428
| 01xx1xxxb | CL-GD5430
| 10xx0xxxb | MGA2
| 10xx1xxxb | CL-GD5440
| 00xx1xxxb | CL-GD5430
| ----------+-----------------
| 10h = PC-9821A-E01 (windows accelerator board A)
| 11h = PC-9801-85 (windows accelerator board B)
| 20h = PC-9821A-E09 (full color window accelerator board A)
| 21h = PC-9801-91 (full color window accelerator board B)
| 60h = PC-9801-96 (window accelerator board B3),
| PC-9801B3-E02 (Microsoft Windows kit)
| 90h = PC-9821A-E11 (window accelerator board A2)
------------------+----------------------------------------------
01h | VRAM window address ■ [PC-9801-96]
| 80h = F20000-F2FFFFh
| A0h = F00000-F0FFFFh
| C0h = F40000 to F4FFFFh
| E0h = F60000 to F6FFFFh
+----------------------------------------------
| Memory-mapped I/O window address
| ■[PC-9821A-E01･09, PC-9801-85･91]
| bit 7: 1MB mode switch
| 1 = Open in memory space of 1MB or more
| 0 = Open in memory space of 1MB or less
| bit 6 to 0: Memory-mapped I/O address
| * When bit 7 is 0, a memory-mapped I/O window is opened in a space of 1MB or less.
| In this case, bit 19 of the memory address is always 1, and the address is specified by bits 6 to 0.
| * When bit 7 is 1, a memory-mapped I/O window is opened in a space of 1MB or more.
| In this case, bits 23 to 19 of the memory address will always be 11111b, and bits 6 to 0 specify the address.
| 40h = 0C0000~0C0FFFh
| 41h = 0C1000~0C1FFFh
| :
| 4Fh = 0CF000～0CFFFFh
| 50h = 0D0000～0D0FFFh
| :
| 5Fh = 0DF000~0DFFFFh
| 60h = 0E0000~0E0FFFh
| :
| 67h = 0E7000~0E7FFFh
| 80h = F80000~F80FFFh
| 88h = F88000~F88FFFh
| 90h = F90000~F90FFFh
| 98h = F98000~F98FFFh
| * Normally, 53h, 57h, 5Bh, 5Fh are used in 15MB mode
| * Normally, 80h, 88h, 90h, 98h are used
| Related I/O 0FA2h, 0FA3h - 02h
------------------+----------------------------------------------
02h | Memory-mapped I/O address
| ■[PC-9821A-E01･09,PC-9801-85･91]
| bits 7-0: Memory-mapped I/O address
| * Address space for memory-mapped I/O
| Specify bits 31-24
| Related I/O 0FA2h,0FA3h - 01h
------------------+----------------------------------------------
03h | Video output switching relay control
| bit 1: Relay control
| ■[PC-9821A-E01･09,PC-9801-85･91]
| 1 = Accelerator output
| 0 = Main unit output through
| bit 0: Memory-mapped I/O control
| ■[PC-9821A-E01･09,PC-9801-85･91]
| 1 = Enable
| 0 = Disabled
------------------+----------------------------------------------
04h | Read dip switch
| bit 7: Interlaced monitor
| 1 = Interlaced monitor
| 0 = Non-interlaced monitor
| bit 6: Model setting ■ [PC-9801-85, 91, 96]
| 1 = PC-98RL, GS, BX2, BS2, BA2
| PC-H98modelS8
| PC-9821 original, Ap, As, Ae, Af, Ce, Bp, Bs, Be
| ･Bf, As2, Ap2
| 0 = PC-9801FX, RS, ES, DS, FS, RA, DA, FA, US, T
| ･CS, BX, BA, PC-98XL^2
| PC-9821Ce2
| * Details unknown
| bit 5: Unused
| bit 4: CPU address mode switch
| ■[PC-9821-E09, PC-9801-91･96]
| 1 = 15MB mode
| 0 = 16MB mode
| bit 3,2: CPU address (16MB mode)
| ■[PC-9821-E09, PC-9801-91･96]
| 00b = F00000-F0FFFFh, F80000-F80FFFh
| 01b = F20000-F2FFFFh, F88000-F88FFFh
| 10b = F40000-F4FFFFh, F90000-F90FFFh
| 11b = F60000-F6FFFFh, F98000-F98FFFh
| bit 1,0: CPU address (15MB mode)
| ■[PC-9821-E09, PC-9801-91･96]
| 00b = E00000-E0FFFFh, 0DF000-0DFFFFh
| 01b = E20000-E2FFFFh, 0DB000-0DBFFFh
| 10b = E40000-E4FFFFh, 0D7000-0D7FFFh
| 11b = E60000-E6FFFFh, 0D3000-0D3FFFh
------------------+----------------------------------------------
05-FFh | Unused
------------------+----------------------------------------------
Explanation o Controls the window accelerator board.
o Reads and writes the register specified by I/O 0FA2h.
Related I/O 0FA2h
I/O 0FAAh
Name Built-in window accelerator control [INDEX]
Undocumented
Target PC-9821Ap2, As2, An (excluding FDD models and models with MGA-II)
PC-9821Xs, Xp, Xn, Ap3, As3
PC-9821Bp, Bs, Be, Bf, Ts, Cs2, Np, Ns, Ne2, Nd, Es, Xe
Function
[READ/WRITE]
Bit 7-0: Window accelerator internal register
Explanation o Controls the built-in accelerator.
o Pairs with I/O 0FABh to perform two-stage I/O operations.
Related I/O 0FABh
I/O 0FABh
Name Built-in window accelerator control [DATA]
Undocumented
Target PC-9821Ap2, As2, An (excluding FDD models and models with MGA-II)
PC-9821Xs, Xp, Xn, Ap3, As3
PC-9821Bp, Bs, Be, Bf, Ts, Cs2, Np, Ns, Ne2, Nd, Es, Xe
Function
[READ/WRITE]
bit 7-0: Data
------------------+----------------------------------------------
Internal register | Contents
------------------+----------------------------------------------
00h | Read ID value
| 00h = PC-9821Ne3, Nd2, Na7, Nx,
| Built-in accelerator for Lt2
| 12h = PC-9821Ap2, As2, An built-in accelerator
| 18h = PC-9821Xs/Xp/Xn/Ap3/As3 built-in accelerator
| 50h = PC-9821Bp/Bs/Be/Bf built-in accelerator
| 51h = PC-9821Cs2 built-in accelerator
| 52h = SV-98model2 built-in accelerator
| 53h = PC-9821Ns built-in accelerator
| 54h = PC-9821Ts built-in accelerator
| 55h = PC-9821Np/Es built-in accelerator
| 56h = PC-9821Ne2 built-in accelerator
| 57h = PC-9821Nd built-in accelerator
| 58h = PC-9821Xe built-in accelerator
| 59h = PC-9821Cb built-in accelerator
| 5Ah = PC-9821Cf built-in accelerator
| 5Bh = PC-9821Xe10, Xa7e, Xb10, PC-9801BX4 built-in Accelerator
| 5Ch = PC-9821Cb2 built-in accelerator
| 5Dh = PC-9821Cx2 built-in accelerator
| 70h = PC-9821Nf built-in accelerator
------------------+----------------------------------------------
01h | Memory-mapped I/O window address
| ■[PC-9821Ap2, As2, An, Xs, Xp, Xn, Ap3, As3]
| 80h = F80000-F80FFFh
| 88h = F88000-F88FFFh
| 90h = F90000-F90FFFh
| 98h = F98000-F98FFFh
+----------------------------------------------
| VRAM window address
| ■[PC-9821Bp･Bs･Be･Bf･Cs2･Ns･Ts･Np･Ne2･Nd･Xe]
| 10h = 0B0000-0BFFFFh
| 80h = F20000-F2FFFFh
| A0h = F00000-F0FFFFh
| C0h = F40000-F4FFFFh
| E0h = F60000-F6FFFFh
| * This value is set by ITF
------------------+----------------------------------------------
02h | VRAM window address
| ■[PC-9821Ap2･As2･An･Xs･Xp･Xn･Ap3･As3]
------------------+----------------------------------------------
03h | Video output switching relay control
| bit 1: Relay control
| ■[PC-9821Ap2･As2･An･Xs･Xp･Xn･Ap3･As3]
| 1 = Accelerator output
| 0 = Main unit output through
| bit 0: Memory-mapped I/O control
| ■[PC-9821Ap2･As2･An･Xs･Xp･Xn･Ap3･As3]
| 1 = Enable
| 0 = Disable
------------------+----------------------------------------------
04h | DIP switch setting
| ■[PC-9821Ap2･As2･An･Xs･Xp･Xn･Ap3･As3]
| bit 7: Interlaced monitor
| 1 = Interlaced monitor
| 0 = Non-interlaced monitor
| bit 6-4: Unused (set to 000b)
| bit 3,2: CPU address
| 00b = F00000-F00FFFh, F80000-F80FFFh
| 01b = F20000-F20FFFh, F88000-F88FFFh
| 10b = F40000-F40FFFh, F90000-F90FFFh
| 11b = F60000-F60FFFh, F98000-F98FFFh
| bit 1,0: Unused (set to 00b)
| * This value is set by ITF
------------------+----------------------------------------------
05-FFh | Unused
------------------+----------------------------------------------
07h | Unknown■[PC-9821Np･Ns･Ne2･Nd･Ap3･As3]
82h | Unknown■[PC-9821Np･Ns･Ne2･Nd]
------------------+----------------------------------------------
83h | DPMS■[PC-9821Np･Ns･Ne2･Nd･Nf]
| bit 1: HSYNC mask
| bit 0: VSYNC mask
| 1 = Do not mask
| 0 = Mask
------------------+----------------------------------------------
8Bh | Unknown■[PC-9821Np･Ns･Ne2･Nd]
------------------+----------------------------------------------
Explanation o Controls the built-in accelerator.
o Reads and writes the register specified by I/O 0FAAh.
Related I/O 0FAAh
I/O 0FACh
Name Display output switching relay control
Undocumented
Target PCI bus equipped models
Function
[READ/WRITE]
Bit 7-2: Unused (always reads 111111b)
Bit 1: Relay control ■ [PC-9821Xa10･Xa9･Xa7･Xa12･Xa7e]
1 = Built-in accelerator
0 = 98 graphics
Bit 0: Relay control
1 = Signal through from RGB IN terminal
0 = Built-in graphics
Explanation o PCI bus equipped models have an RGB IN terminal to switch the
video output of the PCI graphic accelerator card with the output of the
built-in graphics circuit, and this I/O port controls the relay that switches
the display signal output to the RGB OUT terminal.
o When outputting the built-in graphics, the PC-9821Xa10, Xa9, Xa7, Xa12, and
Xa7e are equipped with two relays to select between the output of the built-in
accelerator and the output of the 98 graphics circuit.
o In reality, analog switches may be used instead of relays, but there is no
need to distinguish this from the software perspective.
I/O 0902h
Name CL-GD5428 POS102 Register
Undocumented
Target PC-9801-96
Function
[WRITE]
bit 7,6: Reserved
bit 5: POS 102Access
bit 4-0: Reserved
Explanation o Accesses the I/O of the accelerator chip CL-GD5428.
o Corresponds to the native I/O 0102h of the CL-GD5428.
Related I/O 0FA2h
I/O 0FA3h
I/O 0904h
I/O 0904h
Name CL-GD5428,5430 102Access Control Register
Undocumented
Target CL-GD5428,5430 equipped models
PC-9801-96
Function
[WRITE]
bit 7,6: Reserved
bit 5: POS 102Access
bit 4-0: Reserved
Explanation o Accesses the I/O of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 0094h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O FF82h■[CL-GD5428,5430 equipped machines]
I/O 0902h■[PC-9801-96]
I/O 0CA0h,0C50h
Name CL-GD5428,5430 Attribute Controller Index/Data(Write)
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CA0h)
PC-9801-96 (I/O 0C50h)
Function
[WRITE]
Bit 7-0: Attribute Controller Index/Data
Explanation o Sets the Attribute Controller Data of the accelerator chip
CL-GD5428,5430. The first WRITE specifies the index, and the second WRITE outputs the data.
o Corresponds to the native I/O 03C0h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA1h■[CL-GD5428,5430 equipped machines]
I/O 0C51h■[PC-9801-96]
I/O 0CA1h,0C51h
Name CL-GD5428,5430 Attribute Controller Index/Data(Read)
Undocumented
Target CL-GD5428,5430 equipped machines(I/O 0CA1h)
PC-9801-96(I/O 0C51h)
Function
[WRITE]
bit 7〜0: Attribute Controller Index
[READ]
bit 7〜0: Attribute Controller Data
Explanation o Reads the Attribute Controller Data of the accelerator chip
CL-GD5428,5430. Specify the index with the first WRITE, and read the data by
performing a READ immediately afterwards.
o Supports native I/O 03C1h for CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA0h■[CL-GD5428,5430 equipped machines]
I/O 0C50h■[PC-9801-96]
I/O 0CA2h,0C52h
Name CL-GD5428,5430 Input Status Register 0
CL-GD5428,5430 Miscellaneous Output Register
Undocumented
Target CL-GD5428,5430 equipped machines (I/O 0CA2h)
PC-9801-96 (I/O 0C52h)
Function
[READ]
bit 7: Interrupt Pending
bit 6,5: Reserved
bit 4: DAC Sensing
bit 3〜0: Reserved
[WRITE]
bit 7: Vertical Sync Polarity
bit 6: Horizontal Sync Polarity
bit 5: Page Select
bit 4: Reserved
bit 3,2: Clock Select
bit 1: Enable Display Memory
bit 0: CRTC I/O Address
Explanation o Reads the Status Register 0 of the accelerator chip CL-GD5428,5430.
o Sets the Miscellaneous Output Register of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 03C2h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CACh■[Machines with CL-GD5428,5430]
I/O 0C5Ch■[PC-9801-96]
I/O 0CA3h,0C53h
Name CL-GD5428,5430 Sleep Address Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CA3h)
PC-9801-96 (I/O 0C53h)
Function
[READ/WRITE]
bit 7-5: Reserved
bit 4: Setup
bit 3: Video Subsystem Enable
bit 2-0: Reserved
Explanation o Sets the Sleep Address Register of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 03C3h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA4h,0C54h
Name CL-GD5428,5430 Sequencer Index Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CA4h)
PC-9801-96 (I/O 0C54h)
Function
[READ/WRITE]
bit 7-5: Reserved
bit 4-0: Sequencer Index
Explanation o Sets the Sequencer Index Register of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 03C4h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA5h■[CL-GD5428,5430]
I/O 0C55h■[PC-9801-96]
I/O 0CA5h,0C55h
Name CL-GD5428,5430 Sequencer Data Register
Undocumented
Target CL-GD5428,5430 (I/O 0CA5h)
PC-9801-96 (I/O 0C55h)
Function
[READ/WRITE]
bit 7〜0: Sequencer Data
----------------+----------------------------------------------
SequencerIndex | Contents
----------------+----------------------------------------------
00h | Reset Register
01h | Clocking Mode Register
02h | Plane Mask Register
| Enable Write Pixel Extension
03h | Character MapSelect Register
04h | Memory Mode Register
06h | Unlock ALL Extensions
07h | Extended Sequencer Mode
08h | EEPROM Control
09h | Scratch-Pad 0
0Ah | Scratch-Pad 1
0Bh | VCLK0 Numerator
0Ch | VCLK1 Numerator
0Dh | VCLK2 Numerator
0Eh | VCLK3 Numerator
0Fh | DRAM Control
10h | Graphics Cursor Y
11h | Graphics Cursor X
12h | Graphics Cursor Attributes
13h | Graphics Cursor Pattern Address Offset
14h | Scratch-Pad 2
15h | Scratch-Pad 3
16h | Performance Tuning
17h | Configuration Readback and Extended Control
18h | Signature Generator Control
19h | Signature Generator Result Low Byte
1Ah | Signature Generator Result High Byte
1Bh | VCLK0 Denominator and Post-Scalar Value
1Ch | VCLK1 Denominator and Post-Scalar Value
1Dh | VCLK2 Denominator and Post-Scalar Value
1Eh | VCLK3 Denominator and Post-Scalar Value
1Fh | BIOS ROM Write Enable and MCLK select
----------------+----------------------------------------------
Explanation o Sets the sequencer data register of the accelerator chip CL-GD5428, 5430.
o Reads and writes the register specified by I/O 0CA4h.
o Corresponds to native I/O 03C4h of CL-GD5428, 5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA4h■[CL-GD5428,5430 equipped machines]
I/O 0C54h■[PC-9801-96]
I/O 0CA6h,0C56h
Name CL-GD5428,5430 Pixel Mask Register
CL-GD5428,5430 Hidden DAC Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CA6h)
PC-9801-96 (I/O 0C56h)
Function
[READ/WRITE]
bit 7-0: Pixel Mask7-0
[READ/WRITE]
bit 7: Enable 5-5-5 Mode
bit 6: Enable All Extended Modes
bit 5: Clocking Mode
bit 4: 32K Color Control
bit 3-0: Extended Mode Select
Explanation o Sets the Pixel Mask Register of the accelerator chip CL-GD5428,5430.
o Sets the Hidden DAC Register of the accelerator chip CL-GD5428, 5430.
Access to the Hidden DAC Register is performed after reading the Pixel Mask Register four times.
o Corresponds to the native I/O 03C6h of the CL-GD5428, 5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA7h,0C57h
Name CL-GD5428,5430 Pixel Address Register
CL-GD5428,5430 DAC StateRegister
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CA7h)
PC-9801-96 (I/O 0C57h)
Function
[READ]
bit 7〜2: Reserved
bit 1,0: DAC State
[WRITE]
bit 7〜0: Pixel Address Register(Read Mode)
Explanation o Sets the Pixel Address Register(Read Mode)
of the accelerator chip CL-GD5428,5430. Used when reading the palette.
o Reads the DAC State Register of the accelerator chip CL-GD5428, 5430.
o Supports native I/O 03C7h of the CL-GD5428, 5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA9h■[CL-GD5428,5430 equipped machines]
I/O 0C59h■[PC-9801-96]
I/O 0CA8h,0C58h
Name CL-GD5428,5430 Pixel Address Register
CL-GD5428,5430 DAC State Resgister
Undocumented
Target CL-GD5428,5430 equipped machines (I/O 0CA8h)
PC-9801-96 (I/O 0C58h)
Function
[WRITE]
bit 7-0: Pixel Address Register (Write Mode)
Explanation o Sets the Pixel Address Register (Write Mode)
for the accelerator chip CL-GD5428,5430. Used when setting the palette.
o Corresponds to the native I/O 03C8h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA9h■[CL-GD5428,5430 equipped machines]
I/O 0C59h■[PC-9801-96]
I/O 0CA9h,0C59h
Name CL-GD5428,5430 Pixel Data Register
Undocumented
Target CL-GD5428,5430 equipped machines (I/O 0CA9h)
PC-9801-96 (I/O 0C59h)
Function
[READ/WRITE]
bit 7〜0: Pixel Data Register
Description o Accesses the Pixel Data Register of the accelerator chip CL-GD5428,5430
Used when reading/setting the palette.
o Corresponds to native I/O 03C9h of CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA7h,0CA8h■[CL-GD5428,5430 equipped machines]
I/O 0C57h,0C58h■[PC-9801-96]
I/O 0CAAh,0C5Ah
Name CL-GD5428,5430 Feature Control Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CAAh)
PC-9801-96 (I/O 0C5Ah)
Function
[READ]
bit 7-4: Reserved
bit 3: VSYNC Control
bit 2-0: Reserved
Explanation o Reads the Feature Control Register of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 03CAh of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CACh,0C5Ch
Name CL-GD5428,5430 Miscellaneous Output Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CACh)
PC-9801-96 (I/O 0C5Ch)
Function
[READ]
bit 7: VerticalSyncPolarity
bit 6: HorizontalSyncPolarity
bit 5: PageSelect
bit 4: Reserved
bit 3,2: ClockSelect
bit 1: EnableDisplayMemory
bit 0: CRTC I/O Address
Explanation o Reads the Miscellaneous Output Register of the accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 03CCh of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CA2h■[CL-GD5428,5430 equipped machines]
I/O 0C52h■[PC-9801-96]
I/O 0CAEh,0C5Eh
Name CL-GD5428,5430 Graphics Controller Index Register
Undocumented
Target CL-GD5428,5430 equipped machines (I/O 0CAEh)
PC-9801-96 (I/O 0C5Eh)
Function
[READ/WRITE]
bit 7,6: Reserved
bit 5〜0: Graphics Controller Index
Explanation o Sets the Graphics Controller Index Register of the accelerator chip CL-GD5428,5430.
o Supports native I/O 03CEh for CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CAFh■[CL-GD5428,5430 equipped machines]
I/O 0C5Fh■[PC-9801-96]
I/O 0CAFh,0C5Fh
Name CL-GD5428,5430 Graphics Controller Data Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0CAFh)
PC-9801-96 (I/O 0C5Fh)
Function
[READ/WRITE]
bit 7-0: Graphics Controller Index Data
----------------+----------------------------------------------
Graphics |
ControllerIndex | Contents
----------------+----------------------------------------------
00h | Set/Reset
| Write Mode 5 Background Extension
01h | Set/Reset Enable
| Write Mode 4,5 Foreground Extension
02h | Color Compare
03h | Data Rotate
04h | Read Map Select
05h | Mode
06h | Miscellaneous
07h | Color Don't Care
08h | Bit Mask
09h | Offset Register 0
0Ah | Offset Register 1
0Bh | Graphics Controller Mode Extensions
0Ch | Color Key
0Dh | Color Key Mask
0Eh | Miscellaneous Control
10h | 16bit Pixel Background Color High Byte
11h | 16bit Pixel Foreground Color High Byte
20h | BLT Width Low
21h | BLT Width High
22h | BLT Height Low
23h | BLT Height High
24h | BLT Destination Pitch Low
25h | BLT Destination Pitch High
26h | BLT Source Pitch Low
27h | BLT Source Pitch High
28h | BLT Destination Start Low
29h | BLT Destination Start Mid
2Ah | BLT Destination Start High
2Ch | BLT Source Start Low
2Dh | BLT Source Start Mid
2Eh | BLT Source Start High
2Fh | BLT Write Mask Destination
30h | BLT mode
31h | BLT Start/Status
32h | BLT Raster Operation
34h | Transparent Color Select Low■[CL-GD5428]
35h | Transparent Color Select High■[CL-GD5428]
38h | Transparent Color Mask Low■[CL-GD5428]
39h | Transparent Color Mask High■[CL-GD5428]
----------------+----------------------------------------------
Explanation o Sets the Graphics Controller Data Register
of the accelerator chip CL-GD5428,5430.
o Reads and writes the register specified by I/O 0CAEh.
o Corresponds to native I/O 03CFh of CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0CAEh■[CL-GD5428,5430 equipped machines]
I/O 0C5Eh■[PC-9801-96]
I/O 0DA4h,0D54h
Name CL-GD5428,5430 CRTC Index Register
Undocumented
Target CL-GD5428,5430 equipped machines (I/O 0DA4h)
PC-9801-96(I/O 0D54h)
Function
[READ/WRITE]
bit 7,6: Reserved
bit 5〜0: CRTC Index
Explanation o Sets the CRTC Index Register of the accelerator chip CL-GD5428,5430.
o Supports native I/O 03C4h for CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0DA5h■[CL-GD5428,5430 equipped machines]
I/O 0D55h■[PC-9801-96]
I/O 0DA5h,0D55h
Name CL-GD5428,5430 CRTC Data Register
Undocumented
Target CL-GD5428,5430 equipped models (I/O 0DA5h)
PC-9801-96 (I/O 0D55h)
Function
[READ/WRITE]
bit 7-0: CRTC Data
-----------+----------------------------------------------
CRTC Index | Contents
-----------+----------------------------------------------
00h | Horizontal Total
01h | Horizontal Display End
02h | Horizontal Blanking Start
03h | Horizontal Blanking End
04h | Horizontal Sync Start
05h | Horizontal Sync End
06h | Vertical Total
07h | Overflow
08h | Screen A Preset Row Scan
09h | Character Cell Height
0Ah | Text Cursor Start
0Bh | Text Cursor End
0Ch | Screen Start Address High
0Dh | Screen Start Address Low
0Eh | Text Cursor Location High
0Fh | Text Cursor Location Low
10h | Vertical Sync Start
11h | Vertical Sync End
12h | Vertical Display End
13h | Offset
14h | Underline Row Scanline
15h | Vertical Blanking Start
16h | Vertical Blanking End
17h | Mode Control
18h | Line Compare
19h | Interlace End
1Ah | Interlace Control
1Bh | Extended Display Controls
1Ch | Sync Adjust and Genlock■[CL-GD5430]
1Dh | Overlay Mode Controls
22h | Graphics Data Latches Readback
24h | Attribute Controller Toggle Readback
25h | Part Status
26h | Attribute Controller Index Readback
27h | ID
-----------+----------------------------------------------
Explanation o Sets the CRTC Data Register of the accelerator chip CL-GD5428, 5430.
o Reads and writes the register specified by I/O 0DA5h.
o Corresponds to native I/O 03C5h of CL-GD5428, 5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0DA4h■[CL-GD5428,5430 installed machines]
I/O 0D54h■[PC-9801-96]
I/O 0DAAh,0D5Ah
Name CL-GD5428,5430 Input Status Register1
CL-GD5428,5430 Feature Control Register
Undocumented
Target CL-GD5428,5430 installed machines (I/O 0DAAh)
PC-9801-96 (I/O 0D5Ah)
Function
[READ]
bit 7,6: Reserved
bit 5,4: Diagnostic
bit 3: Vertical Retrace
bit 2,1: Reserved
bit 0: Display Enable
[WRITE]
bit 7〜4: Reserved
bit 3: VSYNC Control
bit 2-0: Reserved
Explanation o Reads the Status Register of the accelerator chip CL-GD5428, 5430.
o Sets the Feature Control Register of the accelerator chip CL-GD5428, 5430.
o Corresponds to the native I/O 03DAh of the CL-GD5428, 5430.
Related I/O 0FAAh
I/O 0FABh
I/O FF82h
Name CL-GD5428,5430 POS102 Register
Undocumented
Target Models with CL-GD5428,5430
Function
[WRITE]
bit 7-1: Reserved
bit 0: Video Subsystem Enable
Explanation o Sets the POS102 Register of the built-in accelerator chip CL-GD5428,5430.
o Corresponds to the native I/O 0102h of the CL-GD5428,5430.
Related I/O 0FAAh
I/O 0FABh
I/O 0904h
===============================================================================
I/O B960h
Name Video capture board control [DATA]
Undocumented
Target PC-9821A-E08, PC-9801-90
Function
[READ/WRITE]
bit 15-0: Data
------------------+----------------------------------------------
Internal register |Contents
------------------+----------------------------------------------
00-FEh | Details unknown
FFh | Read ID value
| 0200h= PC-9801-90
| 0201h= PC-9821A-E08
------------------+----------------------------------------------
Explanation o Details unknown
o Reads and writes the register specified by I/O B962h.
Related I/O B962h
I/O B964h
I/O B962h
Name Video capture board control [INDEX]
Undocumented
Target PC-9821A-E08, PC-9801-90 (Video capture board A, B)
Function
[READ/WRITE]
bit 7-0: Video capture board internal register number
Explanation o Details unknown
o Performs two-stage I/O operation in pairs with I/O B960h.
Related I/O B960h
I/O B964h
I/O B964h
Name Video capture board data transfer
Undocumented
Target PC-9821A-E08, PC-9801-90 (Video capture board A, B)
Function
[READ/WRITE]
bit 31-0: Video data transfer
Explanation o Details unknown
Related I/O B960h
I/O B962h
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